The present invention generally relates to microelectronic devices, and more specifically to a microelectronic integrated circuit with a thin film electrostatic discharge (ESD) protection structure. It further relates to microelectronic packages having ESD protection.
In Metal Oxide Semiconductor (MOS) integrated circuits, input signals are applied to terminals which are connected to gates of MOS Field Effect Transistors (FETs). If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. The dielectric breakdown strength of SiO.sub.2 is approximately 8.times.10.sup.6 volts per centimeter. Thus, a fifteen nm gate oxide will not tolerate voltages greater than twelve volts without breaking down. Although this is well in excess of the normal operating voltages of five-volt integrated circuits, voltages higher than this may be impressed upon the inputs to the circuits during either human-operator or mechanical handling operations.
The main source of such voltages is triboelectricity (electricity caused when two materials are rubbed together). A person can develop a very high static voltage (i.e., a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package, even when careful handling procedures are followed. If such a high voltage is accidentally applied to the pins of an integrated circuit package, its discharge (referred to as electrostatic discharge, or ESD) can cause breakdown of the gate oxide of the devices to which it is applied. The breakdown event may cause sufficient damage to immediately destroy the device, or it may weaken the oxide enough that it will fail early in the operating life of the device, and thereby cause premature device failure.
All pins of MOS integrated circuits must be provided with protective circuits to prevent such voltages from damaging the MOS gates. The need for such circuits is also mandated by the increasing use of VLSI devices in such high noise environments as personal computers, automobiles, and manufacturing control systems.
These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail). Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
The prior art includes four main types of circuits for providing protection against ESD damages, more specifically: diode breakdown, node-to-node punchthrough, gate-field-induced breakdown, and parasitic pnpn diode (thyristor) latchup. These circuits are well known, and thus will not be discussed in detail herein. Often, a combination of protection methods is used, for example a breakdown diode and one of the other protection devices connected in parallel with the gate being protected. See, also International Applications PCT/US95/08808 and PCT/US95/08683, both published on Feb. 1, 1996, as International Publications WO 9602924 ('924) and WO 9602922, ('922), respectively, and hereby incorporated by reference in their entireties.
The prior art ESD protection circuits require that the integrated circuits be provided with additional elements such as diodes and thyristors for each terminal. This reduces the area on the circuits for devices which provide primary logical functionality, and increases the complexity and cost of the integrated circuits.